This invention relates to an integrated circuit and more particularly to an integrated circuit with a body triggered electrostatic discharge protection circuit.
Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A typical circuit used to determine sensitivity of the semiconductor circuit to human handling includes a capacitor and resistor emulate a human body resistor-capacitor (RC) time constant. The capacitor is preferably 100 pF, and the resistor is preferably 1500 xcexa9, thereby providing a 150-nanosecond time constant. A semiconductor device or device under test is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, the capacitor is initially charged to a predetermined stress voltage and discharged through the resistor and the semiconductor device. A post stress current-voltage measurement determines whether the semiconductor device is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge.
A charged-device ESD test is another common test method for testing semiconductor device sensitivity. This method is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The semiconductor device forms a capacitor above a ground plane that is typically 1-2 pF. A low impedance conductor forms a discharge path having an RC time constant typically two orders of magnitude less than a human body model ESD tester. In operation, the semiconductor device is initially charged with respect to the ground plane to a predetermined stress voltage. The semiconductor device is then discharged at a selected terminal through the low impedance conductor. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the semiconductor device approaches that of the initial stress voltage.
Referring to FIG. 1, there is an ESD protection circuit of the prior art including a large multiple finger metal oxide semiconductor (MOS) transistor network (110-118) to conduct the ESD current. This multiple finger MOS transistor is constructed of similar parallel MOS transistors or fingers to withstand high levels of ESD stress current. Under ideal conditions, these MOS transistors generally offer greater ESD protection with increasing transistor width. The common gate terminal 122 of these MOS transistors is grounded by resistor 122 so that they remain off during normal circuit operation.
Referring now to FIG. 2, there is an ideal current-voltage (IV) characteristic of an individual MOS transistor. The IV characteristic shows that negligible drain-source current (IDS) flows through the MOS transistor while drain-source voltage (VDS) is less than the avalanche voltage (VA). When voltage across the MOS transistor exceeds VA as during an ESD pulse, the drain-source voltage VDS decreases to snap back voltage VSB. This snap back is similar to a transition from the open-emitter collector-base breakdown voltage (BVCBO) to the open-base collector-emitter breakdown voltage (BVCEO) of a bipolar transistor. Any subsequent increase in VDS significantly increases IDS. A common problem with these ESD protection circuits of the prior art, however, arises due to slight variations of the IV characteristic with each MOS transistor due to process and layout variations. When one of the MOS transistors, for example transistor 110, begins conducting prior to the other transistors (112-118), it snaps back to region 200. Transistors 112-118 have a common VDS with transistor 110 and return to region 202. Transistors 112-118, therefore, conduct negligible ESD current. Transistor 110, however, conducts virtually all the ESD current. This current hogging reduces the effective width of the protection circuit to the width of transistor 110, thereby reducing the corresponding failure threshold of the semiconductor device.
Alternative protection circuit designs of the prior art have attempted to overcome this problem by increasing the value of resistor 120, thereby permitting the voltage at common gate electrode 122 to increase by capacitive coupling with application of an ESD pulse. This method of triggering the MOS device, however, requires time to form of an MOS inversion layer and begin avalanche conduction in the pinch-off region of the channel prior to conduction. Other circuit designs have included individual resistors (not shown) in series with each corresponding transistor 110-118. These individual resistors decrease the slope of the curve at region 206 so that the voltage at region 204 exceeds avalanche voltage VA. This advantageously prevents a premature transition of any transistor into second breakdown and ensures that all parallel transistors will eventually turn on. This method, however, requires an even greater time for each transistor to turn on and may result in premature failure of individual transistors before all transistors begin conduction. Thus, none of the protection circuit methods of the prior art offer a satisfactory turn on time required for fast ESD pulses such as the charged-device test pulse.
These problems are resolved by a protection circuit with an external terminal, a reference terminal and a substrate. A semiconductor body is formed by an isolation region formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal connected to a common control terminal and a respective current path connected between the external terminal and the reference terminal. A capacitor is connected between the semiconductor body and the external terminal. A resistor is connected between the semiconductor body and the reference terminal.
The present invention provides fast activation of an ESD protection circuit by capacitively coupling a fraction of an ESD stress voltage to the semiconductor body. Parallel protection transistors are uniformly activated and resistance is minimized.